FPGA Design Engineer (RTL/ VHDL / Verilog)

Job type Full-time
  • Experience: 2-5 years
  • Location: Ahmedabad
  • Educational Qualification: B.E/ B.Tech/ M.Tech in Electronics /Embedded Systems /VLSI.

Key Responsibilities

  • Design and implement hardware and RTL code using VHDL / Verilog.
  • Develop FPGA modules for sensor interface, high-speed data capture, buffering, and transmission.
  • Implement communication interfaces such as SPL UART, LVDS, DDR, Ethernet.
  • Perform functional simulation and timing analysis..
  • Optimize designs for performance, latency, and resource utilization.
  • Debug FPGA designs using logic analyzers and hardware tools.
  • Work closely with hardware and embedded software teams.

Required Skills

  • Strong experience in RTL development (VHDL/Verilog).
  • Experience with FPGA tools
  • Knowledge of high-speed digital interfaces.
  • Familiarity with image sensor data pipelines (preferred).
  • Experience with simulation tools.